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<!--sram_8_256_sky130A,256,1,1,0,0,sky130A,25,1.8,TT,7.617,/home/xiaoyu/Projects/vostok564/ASIC-SKY130/RAMGen/ram08256/,/home/xiaoyu/Projects/vostok564/ASIC-SKY130/RAMGen/ram08256/sram_8_256_sky130A_TT_1p8V_25C.lib,8,0589a35f7315fc075eaca38c0abd477703e70bf7,2021-10-08,True,5002,3,81661.77440000001,din0[7:0],0.009,0.009,0.009,0.009,0.001,0.001,0.001,0.001,dout0[7:0],1.856,2.059,1.856,2.059,0.007,0.027,0.007,0.027,csb0,0.009,0.009,0.009,0.009,0.001,0.001,0.001,0.001,addr0[7:0],0.009,0.009,0.009,0.009,0.001,0.001,0.001,0.001,web0,0.009,0.009,0.009,0.009,0.001,0.001,0.001,0.001,power,!csb0 & clk0 & !web0,Read,0.9894297536467194,power,!csb0 & !clk0 & web0,Write,0.9894297536467194,leak,csb0,0.002318,sim_time,0.19061851501464844,words_per_row,8,slews,[0.0125, 0.05, 0.4],loads,[2.45605, 9.8242, 39.2968],cell_rise_0,[1.8556055072627609, 1.896215557197761, 2.058655756937761, 1.8556055072627609, 1.896215557197761, 2.058655756937761, 1.8556055072627609, 1.896215557197761, 2.058655756937761],cell_fall_0,[1.8556055072627609, 1.896215557197761, 2.058655756937761, 1.8556055072627609, 1.896215557197761, 2.058655756937761, 1.8556055072627609, 1.896215557197761, 2.058655756937761],rise_transition_0,[0.006513659918468256, 0.010574664911968254, 0.026818684885968253, 0.006513659918468256, 0.010574664911968254, 0.026818684885968253, 0.006513659918468256, 0.010574664911968254, 0.026818684885968253],fall_transition_0,[0.006513659918468256, 0.010574664911968254, 0.026818684885968253, 0.006513659918468256, 0.010574664911968254, 0.026818684885968253, 0.006513659918468256, 0.010574664911968254, 0.026818684885968253],write_rise_power_0,1.9788595072934392,write_fall_power_0,1.9788595072934392,read_rise_power_0,1.9788595072934392,read_fall_power_0,1.9788595072934392,END
--><a href="https://vlsida.soe.ucsc.edu/"><img src="" alt="VLSIDA"></a><a href ="https://github.com/VLSIDA/OpenRAM"><img src ="" alt = "OpenRAM"></a><p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">sram_8_256_sky130A.html</p><p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Compiled at: 2021-10-08</p><p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">DRC errors: 5002</p><p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">LVS errors: 3</p><p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Git commit id: 0589a35f7315fc075eaca38c0abd477703e70bf7</p><p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Ports and Configuration</p><table id= "data"><thead><tr><th>Type</th><th>Value</th></tr></thead><tbody><tr><tr><td>WORD_SIZE</td><td>8</td></tr><tr><td>NUM_WORDS</td><td>256</td></tr><tr><td>NUM_BANKS</td><td>1</td></tr><tr><td>NUM_RW_PORTS</td><td>1</td></tr><tr><td>NUM_R_PORTS</td><td>0</td></tr><tr><td>NUM_W_PORTS</td><td>0</td></tr><tr><td>Area (&microm<sup>2</sup>)</td><td>81662</td></tr></tr></tbody></table>
<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Operating Conditions</p><table id= "data"><thead><tr><th>Parameter</th><th>Min</th><th>Typ</th><th>Max</th><th>Units</th></tr></thead><tbody><tr><tr><td>Power supply (VDD) range</td><td>1.8</td><td>1.8</td><td>1.8</td><td>Volts</td></tr><tr><td>Operating Temperature</td><td>25</td><td>25</td><td>25</td><td>Celsius</td></tr><tr><td>Operating Frequency (F)</td><td></td><td></td><td>131</td><td>MHz</td></tr></tr></tbody></table>
<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Timing Data</p><p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Using analytical model: results may not be precise</p><table id= "data"><thead><tr><th>Parameter</th><th>Min</th><th>Max</th><th>Units</th></tr></thead><tbody><tr><tr><td>din0[7:0] setup rising</td><td>0.009</td><td>0.009</td><td>ns</td></tr><tr><td>din0[7:0] setup falling</td><td>0.009</td><td>0.009</td><td>ns</td></tr><tr><td>din0[7:0] hold rising</td><td>0.001</td><td>0.001</td><td>ns</td></tr><tr><td>din0[7:0] hold falling</td><td>0.001</td><td>0.001</td><td>ns</td></tr><tr><td>dout0[7:0] cell rise</td><td>1.856</td><td>2.059</td><td>ns</td></tr><tr><td>dout0[7:0] cell fall</td><td>1.856</td><td>2.059</td><td>ns</td></tr><tr><td>dout0[7:0] rise transition</td><td>0.007</td><td>0.027</td><td>ns</td></tr><tr><td>dout0[7:0] fall transition</td><td>0.007</td><td>0.027</td><td>ns</td></tr><tr><td>csb0 setup rising</td><td>0.009</td><td>0.009</td><td>ns</td></tr><tr><td>csb0 setup falling</td><td>0.009</td><td>0.009</td><td>ns</td></tr><tr><td>csb0 hold rising</td><td>0.001</td><td>0.001</td><td>ns</td></tr><tr><td>csb0 hold falling</td><td>0.001</td><td>0.001</td><td>ns</td></tr><tr><td>addr0[7:0] setup rising</td><td>0.009</td><td>0.009</td><td>ns</td></tr><tr><td>addr0[7:0] setup falling</td><td>0.009</td><td>0.009</td><td>ns</td></tr><tr><td>addr0[7:0] hold rising</td><td>0.001</td><td>0.001</td><td>ns</td></tr><tr><td>addr0[7:0] hold falling</td><td>0.001</td><td>0.001</td><td>ns</td></tr><tr><td>web0 setup rising</td><td>0.009</td><td>0.009</td><td>ns</td></tr><tr><td>web0 setup falling</td><td>0.009</td><td>0.009</td><td>ns</td></tr><tr><td>web0 hold rising</td><td>0.001</td><td>0.001</td><td>ns</td></tr><tr><td>web0 hold falling</td><td>0.001</td><td>0.001</td><td>ns</td></tr></tr></tbody></table>
<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Power Data</p><table id= "data"><thead><tr><th>Pins</th><th>Mode</th><th>Power</th><th>Units</th></tr></thead><tbody><tr><tr><td>!csb0 & clk0 & !web0</td><td>Read Rising</td><td>0.9894</td><td>mW</td></tr><tr><td>!csb0 & clk0 & !web0</td><td>Read Falling</td><td>0.9894</td><td>mW</td></tr><tr><td>!csb0 & !clk0 & web0</td><td>Write Rising</td><td>0.9894</td><td>mW</td></tr><tr><td>!csb0 & !clk0 & web0</td><td>Write Falling</td><td>0.9894</td><td>mW</td></tr><tr><td>csb0</td><td>leakage</td><td>0.002318</td><td>mW</td></tr></tr></tbody></table>
<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Characterization Corners</p><table id= "data"><thead><tr><th>Transistor Type</th><th>Power Supply</th><th>Temperature</th><th>Corner Name</th></tr></thead><tbody><tr><tr><td>TT</td><td>1.8</td><td>25</td><td>_TT_1p8V_25C.lib</td></tr></tr></tbody></table>
<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Deliverables</p><table id= "data"><thead><tr><th>Type</th><th>Description</th><th>Link</th></tr></thead><tbody><tr><!--.db<tr><td>.db</td><td>Compiled .lib</td><td><a href="sram_8_256_sky130A_TT_1p8V_25C.db">sram_8_256_sky130A_TT_1p8V_25C.db</a></td></tr>.db--><tr><td>.gds</td><td>GDSII layout views</td><td><a href="sram_8_256_sky130A.gds">sram_8_256_sky130A.gds</a></td></tr><tr><td>.html</td><td>This datasheet</td><td><a href="sram_8_256_sky130A.html">sram_8_256_sky130A.html</a></td></tr><tr><td>.lef</td><td>LEF files</td><td><a href="sram_8_256_sky130A.lef">sram_8_256_sky130A.lef</a></td></tr><tr><td>.lib</td><td>Synthesis models</td><td><a href="sram_8_256_sky130A_TT_1p8V_25C.lib">sram_8_256_sky130A_TT_1p8V_25C.lib</a></td></tr><tr><td>.log</td><td>OpenRAM compile log</td><td><a href="sram_8_256_sky130A.log">sram_8_256_sky130A.log</a></td></tr><tr><td>.py</td><td>OpenRAM configuration file</td><td><a href="sram_8_256_sky130A.py">sram_8_256_sky130A.py</a></td></tr><tr><td>.sp</td><td>SPICE netlists</td><td><a href="sram_8_256_sky130A.sp">sram_8_256_sky130A.sp</a></td></tr><tr><td>.v</td><td>Verilog simulation models</td><td><a href="sram_8_256_sky130A.v">sram_8_256_sky130A.v</a></td></tr></tr></tbody></table>
